very good with strong distorted cahnnel where noise is also

amplified with symbols at higher frequencies resulting in Inter symbol

Interference (ISI). To over come these limitations DFEs are used. DFEs use the

feedback of the received symbol to produce the estimated channel output. Thus

DFE is fed with detected symbols and produces an estimated output which is

subtracted from the output of linear equalizer.

Fig.2 Reformulated DFE for 2nd

order FBF

Fig

2 shows the architecture of conventional adaptive DFE. It consists of two FIR

filters namely Feef forward Filter and Feedback FIlter. L and N are their

orders respectively.The operation of DFE can be explained with the following

sets of equation:

?n

= fnTxn ?

bnTdn

(1a)

en

= ? n ?

?n

(1b)

?n

= Q?n

(1c)

Fn+1=

fn + µenxn

(1d)

bn+1

= bn + µ endn

(1e)

where n is the current time

instance, xn is the vector of received samples, dn is the

vector of detected samples fn if FFF coefficient vector, bn

is the FBF coefficient vector.The critical path of DFE is shown by the dashed

line which consists of multipliers two adders and a slicer.to reduce the

computational complexity two adders are replaced by the carry save full adder

and two input adder.Using TSMC 90nm CMOS standard the values od computational

delay of multipler, adder and slicer are found to be 1.54ns,0.74ns and 0.05ns

respectively.In this case the critical path estimated as 1.20 ns which is below

the throughput requirement of 5G. to overcome this limitation relaxed lookahead

DFE is used.It is similar to conventional DFE but it has an extra register in

the decision feedback loop to speedup the architecture by the factor of 2.The

architectural diagram of relaxed look ahead DFE is shown below.

Fig.3.

Architectural diagram with relaxed look ahead DFE

HIGH SPEED DFE SCHEMES

To reduce the computational complexity the feedback and

feedforward filter coefficients are stored in separate LUT and rapidly updated.

This process is done in two stages, hence it is called two stage precomputation

DFE. In first stage only few FBF coefficients are precomputed and saved in

separate LUT1 which reduced the multiplier complexity. In case of

PP-DFE (partially precomputed DFE) it is found that the remaining multipliers

are still high and occupies more area. This can be solved by precomputing and

storing the remaining multiplier coefficients in another LUT2 at

stage 2. Thus hardware and computational complexities are reduced.

PROPOSED METHOD

In this method first the LUT1 and LUT2

are transformed and then the proposed architecture is rescaled and unfolded to

achieve the higher throuhput.Now the content of LUT2 is reduced to

half the size by rescaling.This is done with the sign reversal operation for

the remaining content.Now the contents of LUT1 will disturb the

symmetry. Now by adding the FFF output minor symmetry can be achieved. Now

similar to LUT2 ,LUT1 is transformed.Thus the LUT of

stage 1 and 2 are reduced to half.by combining these LUT with DFE our proposed

architechture is obtained.The iteration bond of the proposed architechture

decreases with the larger order of the filter.Thus it reduces the hardware

complexity.Generally it is difficult to store the output of FFF in LUT since

the LUT has to be dynamically updated and the output is larger which consumes

more power and time. But by adding the FFF output outside the LUT in our

proposed mrthos these limitations are overcomed.

Fig.4. Proposed

Architecture